This camera design is the highest resolution camera Fishcamp Engineering has designed. It utilizes a 59MPixel CMOS Image sensor that is capable of running up to 10 frames per second. Total pixel rates on this camera approached 600MPixels/sec.

In order to support the pixel rates this camera is capable of producing, we utilized four, individual, CameraLink interface ports. An optional mode allowed us to operate with all pixel data multiplexed over only two of the CameraLink interfaces. This reduced the cabling requirements between the camera and host resident frame grabber. The CameraLink port functionality was implemented entirely in FPGA resident logic thus reducing the power and size requirements that would have been needed if we had used traditional, discrete, CameraLink SERDES interface chips.

The power supply board for the camera included the capability to provide a controlled power source for a TEC cooler module used to stabilize the operating temperature of the Image Sensor chip. An embedded uP implemented in an FPGA was used to monitor and control the set-point temperature of the sensor.

The image processor circuit card assembly included the FPGA chips and support circuitry as well as the CameraLink interface connectors. The printed circuit card design was implements with rigid-flex technology in order to minimize the space and reliability problems associated with traditional inter-board connector arrangements.

All sensor timing, pixel formatting, and buffering logic was implemented within the FPGAs on the card with two such cards required for each camera.