This board was the digital baseband processor for a 26GHz LMDS fixed wireless, internet access terminal. On the front end, a DOCSIS compliant cable interface was used to provide the user data source for transmission across the wireless link. Four Xilinx FPGAs (2M gates each) were used to perform all of the digital signal processing to up convert the DOCSIS signal to the IF interface to the rest of the radio subsystems.

An embedded PowerPC CPU (running WindRiver's VxWorks) was used for station keeping functions and inter-terminal supervisory communications.

Fishcamp Engineering was responsible for the board level design as well as the FPGA logic that interfaced with the board level interface chips.