This design was the key subsystem in a video effects imaging system. Besides the custom interface to a high end image sensor, the assembly included standard VGA and NTSC video interfaces. Multiple, independent banks of SDRAM provided for a total memory bandwidth of 3.2GByte/sec.

A 4M gate FPGA was used to perform the video image processing functions. Utilizing a deep pipeline architecture, the logic was able to perform parallel math operations in real-time to keep up with a 200 frame/sec video rate.